PROGRAM
Thursday, September 28 (Day 2)
PRESENTATIONS
09:00–09:45
SEMICONDUCTOR ECO-SYSTEM
About Brains, Semicons and Presentations
We all have a story to tell - especially in sales presentations. But all too often we get lost in our own story and lose sight of the most important thing: our audience. In this refreshing first hour of Day Two, we'll take a look at what makes good presentations and uncover one of the most common misconceptions.
Biography
Roman Gramse holds a Master of Arts degree in Design. He is co-founder, head of product management and head of corporate communications at a cloud software provider for the hospitality industry. For more than 15 years, he has also worked as a freelance management consultant, is involved in several startups and is a lecturer at the University of Bremen in the Department of Communication and Media Studies.
09:45–10:00
SEMICONDUCTOR ECO-SYSTEM
Dutch Semicon and Quantum Technologies
The Dutch semiconductor industry has brought many groundbreaking innovations to market. This sector is pulled forward by multiple leading Original Equipment Manufacturers, and relies on a strong infrastructure of knowledge institutes and world leading (module) suppliers. Examples mentioned in this presentation show the depth and width of this ecosystems and its portfolio in semiconductor equipment, including recent extensions into the emerging PIC and quantum technologies.
Biography
Dr. Rogier Verberk holds a PhD in experimental physics from Leiden University (2005). At TNO he worked on EUV lithography with ASML and Carl Zeiss and became principal project manager. From 2013 on he helped to set up the QuTech research centre for quantum technologies. Since 2016 he is Market Director at TNO responsible for Semiconductor Equipment, Quantum Technologies, and Medical Photonics. He is active as core team member of the Dutch national roadmaps for Nanotechnology and Semiconductor Equipment, the Strategic Advisory Board of the European Quantum Technologies Flagship, and Supervisory Board member of QuantumDeltaNL.
10:00–10:30
NEW PRODUCTS & TRENDS
Salland roadmap and new products
- abstract will be available shortly -
Biography
Paul van Ulsen
Paul has over 37 years’ experience in Semiconductor Test and is currently responsible for all aspects of corporate governance and business development for Salland Engineering worldwide. He is a graduate of Windesheim Technical University in electronics and computer engineering.
In 1986, Paul started his career as Test Application engineer at Rood Testhouse, where he was involved in many Mixed Signal test solutions. In 1992, he continued as Application engineer at Salland and moved soon into new roles like; project management, HR and Sales which made him decide to choose to be the Sales Director, followed becoming the CEO and in 2017 the owner of Salland Engineering world-wide. In 2018 he acquired Applicos, a leading Analog post-silicon-validation test solution provider, and successfully integrated this into Salland family. In meantime he guided Salland, together with his team, being a worldwide leading and respected player & partner of all top ATE manufactures and being a very advanced and fast(est) growing Engineering & Production Testhouse.
Armando Bonilla Fernandez
Armando has a Bachelor degree in Mechatronics from the UANL in Mexico with 3 years of experience in industrial automation. He received the MSc degree in electrical engineering from the University of Twente, Enschede, The Netherlands, in 2016, with specialization in Robotics and Mechatronics. In 2017 he joined Salland Engineering (Europe) B.V. where he focuses on Design Verification of electronic instrumentation and hardware design.
10:30–11:00
NEW PRODUCTS & TRENDS
Future trends in lithography
ASML’s EUV scanner has taken the world by storm – EUV is at the core of the newest chips and of geopolitical rivalries. The chips made with EUV outperform their DUV equivalents, and all chips made on newer nodes require several steps of EUV for their smallest features. The short wavelength of the EUV light – 13.5nm – is the key to printing such small features. But working with this wavelength is also incredibly challenging: Not only is a completely new light source required – moving from ArF and KrF excimer lasers to Sn-based laser-produced-plasma, also all optical components had to be re-invented. Traditional lenses no longer work at 13.5 nm – as glass is not transparent at that wavelength. Mirrors with atomically perfect multilayer coatings had to be developed – and while Zeiss developed the mirrors in Southern Germany, the coatings were developed right here, in Enschede. These coatings require atomically perfect layers and interfaces in order to reflect the EUV light in a world where every % of reflectivity, and hence scanner throughput counts. I will show how the XUV group at the University of Twente developed these multilayer coatings, and how today we still push to improve every optical element in the EUV scanner.
Biography
Marcelo Ackermann is chair of the Industry Focus Group – X-ray and EUV (XUV) optics at the MESA+ institute of University of Twente. He obtained his PhD in physics (cum laude) in 2007 on a shared research project between Leiden University and the ESRF in Grenoble, under the guidance of Prof J.W.M Frenken and Prof. S. Ferrer. After that held different leading positions in industrial research for the development of X-ray, visible and IR optics for companies like cosine Research, Helbling Technik, SCHOTT Advanced Optics and ASML. In 2020 he re-joined academic research as full professor in the XUV optics group, focussing on the development of next generation reflective, refractive and transparent X-ray and EUV optics in collaboration with industrial partners like Zeiss SMT, ASML and Malvern Panalytical.
11:00–11:15
SHORT BREAK WITH VENDOR FAIR
11:15–11:45
PRODUCT SUPPLY CHAIN
Phazor RF Probe Solutions for Next Generation RF upto 110Ghz
During this session we will elaborate on enabling new wafer probe solutions by utilizing MEMS technologies to deliver enhanced RF and high power capabilities.
Biography
Gordon joined PTSL as R&D Manager in 2020, and currently holds the position to Director of Test and Field Applications Engineering. Gordon has over 25 years of continuous service in the semiconductor test industry. Across his career, Gordon’s technical acumen and ability to derive new technology and techniques for the ever changing needs of the Industry are part of his key strengths in delivering 1st in class test solutions to internal and external customers. Gordon graduated in Electrical and Electronic Engineering from Glasgow Caledonian University. Gordon also holds an international patent in relation to MEMS testing.
11:45–12:15
PRODUCT SUPPLY CHAIN
Relay selection considerations for the future of high-density probe solutions
This presentation delves into relay selection in the high-density test market, driven by the evolving landscape of 5G, IoT, AI, and autonomous vehicles, resulting in complex ICs and increased testing demand. Two critical market pressures emerge: accommodating more DUTs per touchdown, creating space, speed, and thermal challenges, and the growing IC complexity, necessitating additional test circuits and emphasizing the need to reduce time to yield for semiconductor test firms. Relay selection plays a pivotal role in addressing these challenges. We evaluate traditional options like electromechanical, reed, solid-state, and emerging MEMS relays, considering their pros and cons. Atomica, with its expertise in custom MEMS wafer processing and the development of an innovative MEMS relay platform, offers unique insights. A deep dive into MEMS relays explores how they alleviate PCB space, speed, thermal constraints, and test throughput challenges. Atomica, as a technology expert, identifies scenarios where MEMS may not be ideal and outlines future considerations from its platform pipeline.
Biography
Eric Bower
Eric is the Account Executive at Atomica where he leads sales for Atomica’s MEMS Relay platform, partnering on design-win opportunities with ATE, IoT, medical device and consumer electronics applications. Previously, he was a member of the foundry services business development team at Atomica where he evaluated novel MEMS sensors, photonics, and biochip projects from startups and Fortune 500 companies. Before Atomica, Eric has experience as a sustainability analyst for Voiz, a decentralized product review and education startup. He has a Bachelor of Science Degree in Environmental Science and Technology Management from the University of California, Santa Barbara.
Seena Partokia
Seena is the Vice President of Product Development at Atomica and oversees R&D initiatives. Has has worked on switches of all kinds his entire career such as Silicon on Sapphire, Silicon on Insulator, and Cantilever MEMS on fused silica during various product engineering roles at Peregrine Semiconductor, Silanna Semiconductor (acquired by Qualcomm for leading front-end RF switch technology) and Menlo Microsystems. Seena has developed innovative bonding, layer transfer, and via technologies to be introduced on novel products with order of magnitude figure of merit advantages to the market. He has Bachelor of Science Degree in Electrical Engineering with a focus on solid-state devices and photonics from the University of California, San Diego.
12:15–12:45
PRODUCT SUPPLY CHAIN
A Testing Perspective on Scaling Integrated Photonics to High Volumes
Artificial Intelligence and High-Performance Computing are accelerating the demand for next-generation optical interconnects, with photonic integrated circuits as one of the key enablers of this (r)evolution. These wafer-based technologies are ideal for high channel count and high-density optical interconnects such as Co-Packaged Optics but have unique challenges. This presentation will discuss the testing challenges and solutions of scaling PIC technology to the desired volumes.
Biography
Kees has over 20 years’ experience in product management and technology marketing and is currently Vice President Marketing / General Manager Quantifi Photonics USA Inc., a company specializing in testing next-generation optical interconnect technology such as Silicon Photonics and Co-Packaged Optics. After starting his career in integrated photonics research and development he moved into product management at JDS Uniphase. A shift into test and measurement led to his role as manager of Tektronix’s application engineering team in Silicon Valley, before joining MultiLane as Vice President Marketing and General Manager Measurement Solutions.
He gained a Master of Science in physics and a post-graduate degree in modern optics from the University of Twente in the Netherlands.
12:45–13:30
LUNCH WITH VENDOR FAIR
13:30–14:00
GROUP PHOTO
14:00–14:30
AUTOMATED TEST
Solving the challenges of the next generation of SLT tests
System level testing (SLT) allows testing an IC under its end application environment. The approach is widely preferred as the IC is tested in a module board setup similar to the module board found in the electronic devices. However, since both wafer manufacture and packaging technologies are advancing, testing solution providers are facing more and more challenges especially regarding higher heat dissipation, yield control, temperature control on different zones of IC and junction temperature feedback of course. The session also focuses on the solutions offered by chroma for system level testing, we are going to share with you how do we co-work with tier one customers on resolving their difficulties and advance together.
Biography
Herbert Tsai is currently the Vice President of Chroma ATE Inc with over 27+ years of experience in the semiconductor industry. He holds more than 30+ patents in semiconductor testing. Prior to joining Chroma ATE Inc, Mr. Tsai was the Vice President of TASK Technology where he held key R&D roles and was responsible for technology development and strategies at SLT auto test handler. During his tenure at Chroma ATE Inc, he contributed to the development of new testing solutions in SLT, thermal engine, CIS sensor, and i4.0 automation. His work in SLT and CIS turnkey solutions has sustained pioneering and leading techniques that play a trend-setting role in the market. Mr. Tsai holds a mechanical engineering degree from the College of Naya.
14:30–15:00
AUTOMATED TEST
Revolutionizing High-Parallel MEMS Sensor Testing with Cohu's Sense+ Handler
This presentation explores Cohu's Sense+ MEMS Handler, which is revolutionizing high-parallel testing for MEMS sensors in both strip and batch formats.
In the first section, we trace the evolution from singulated testing to batch testing in the backend testing process for MEMS sensors. We highlight the remarkable capabilities of this evolution and its pivotal role in significantly enhancing testing efficiency and Quality. The second section highlights the intricate challenges associated with contacting MEMS sensors, especially in gyroscopic applications. We delve into cost-effective solutions, underscore the importance of continuous performance monitoring, and introduce innovative methods designed to ensure optimal sensor performance throughout its entire lifespan. We invite you to join us at the conference for a deeper exploration of these advancements that are reshaping the landscape of MEMS sensor testing.
Biography
Alex Waldauf was one of the founders of Cohu’s Rasco GmbH business unit in 1998 and has been Cohu’s Director of Product Marketing Management since June 2020. Mr. Waldauf was previously Vice President of Platform Engineering from June 2017 to May 2020, and Vice President and General Manager from January 2011 to May 2017. Mr. Waldauf has also held various management positions in engineering and sales. Prior to joining Cohu Mr. Waldauf spent six years at Multitest, where he held key positions in RnD & Mr. Waldauf holds a Mechanical Engineering degree from the Austrian School of Technology in Salzburg (HTL).
15:00–15:30
AUTOMATED TEST
Efficient support of scan bus architectures and packetized scan test on Advantest V93000
SCAN bus architectures and packetized scan test are the current state of the art for efficient parallel scan test of multiple cores. This type of DfT architecture can significantly boost production test throughput and provides substantial advantages for parallel test of both homogeneous and heterogeneous cores. It is currently being deployed on many large digital designs. On the tester, it helps to bridge the bandwidth gap between (fast) digital channel speed and (slow) device internal scan shift speed, which is very relevant to keep test pattern execution times under control. However, there are also new requirements for the test program implementation, both on the test setup and result side. This presentation will give a short introduction to packetized scan test and then focus on the relevant details for the test program implementation on Advantest V93000.
Biography
Michael has over 20 years experience in the ATE industry and holds a Master degree in Electrical Engineering from the University of Mannheim, Germany. Within Advantest he started as a V93000 application engineer and has several years experience as a Solution Architect in R&D. Currently he holds the position of Product Manager with focus on Digital test, DfT, new test methodologies and EDA / ATE collaboration.
15:30–16:00
AUTOMATED TEST
From 5G mmWave to 6G THz: High-volume Handler-based OTA Testing of AiP Devices
mmWave devices are proliferating throughout the industry, across many applications, thanks to the benefits of beamforming made possible by AiP solutions. This presentation provides an overview of the process and tools currently available for developing handler-based OTA testing solutions that are suitable for high-volume production. There are multi-site solutions ready for production today that offers OSATs and end-customers the ability to improve mmWave module performance and final test yields for applications such as 5G mmWave, automotive radar, satellite internet, and eventually, 6G THz.
Biography
Dr. Jeorge S. Hurtarte is currently Senior Director of Product Marketing in the Semiconductor Test group at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. He is a voting member of the IEEE 802.11 Wi-Fi standards committee and serves as the secretary of the IEEE 802.11ay task group. Jeorge is currently the co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Working Group, and a visiting professor at the University of California, Santa Cruz and the University of Phoenix.
16:00–17:00
CLOSING DRINKS