PROGRAM
Wednesday, September 27 (Day 1)
PRESENTATIONS
09:30–10:00
KEYNOTE
Sallands vision on the Future of Test
Opening of the Symposium and welcome speech by Paul van Ulsen, CEO and owner of Salland Engineering, where he will share Salland's vision on the future of semiconductor test.
Biography
Paul has over 37 years’ experience in Semiconductor Test and is currently responsible for all aspects of corporate governance and business development for Salland Engineering worldwide. He is a graduate of Windesheim Technical University in electronics and computer engineering.
In 1986, Paul started his career as Test Application engineer at Rood Testhouse, where he was involved in many Mixed Signal test solutions. In 1992, he continued as Application engineer at Salland and moved soon into new roles like; project management, HR and Sales which made him decide to choose to be the Sales Director, followed becoming the CEO and in 2017 the owner of Salland Engineering world-wide. In 2018 he acquired Applicos, a leading Analog post-silicon-validation test solution provider, and successfully integrated this into Salland family. In meantime he guided Salland, together with his team, being a worldwide leading and respected player & partner of all top ATE manufactures and being a very advanced and fast(est) growing Engineering & Production Testhouse.
10:00–10:30
IC DESIGN & TEST CHALLENGES
Tessent™ Streaming Scan Networks (SSN): An Introduction for Test & Product Engineers
The increasing complexity in large System on Chip (SoC) designs presents challenges to all IC design disciplines, including design-for-test (DFT), Product & Test Engineering. Tessent™ Streaming Scan Network (SSN) is a system for packetized delivery of scan test patterns. It enables simultaneous testing of any number of cores with few chip-level pins and reduces test time and test data volume. With SSN, DFT engineers now have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. It can test any number of identical core instances in near-constant time, minimizes padding in the presence of cores with mismatched pattern counts and/or scan chain lengths and enables fast streaming of data to/from and throughout the chip. It simplifies design planning and implementation and is especially well suited for tile-based designs.
This presentation describes the basic components of the Tessent™ Streaming Scan Network and highlights some of the key benefits for Test & Product Engineers with respect to bring-up and volume manufacturing including:
- Reduced pattern counts, test volume and test cost
- Efficient testing of duplicate cores
- Flexibility of test scheduling & execution
- Improved power and IR-Drop profiles
- Diagnostics support
Biography
Chris Dodd is a Senior DFT Architect at Siemens EDA and has over 30 years experience within the Semiconductor industry. He has worked across several fields including Device Engineering, Failure Analysis, Test & Product Engineering, Project Management & Design-For-Test with the likes of Motorola, Cadence, Atmel, Wolfson, Cirrus Logic, Graphcore Ltd & Siemens EDA . This journey has encompassed a wide range of semiconductor segments covering automotive, HPC & AI and consumer. Chris graduated in 1992 with a 1st Class Joint Honours in Physic & Electronics from Glasgow University and holds an MBA from Strathclyde University.
10:30–11:00
IC DESIGN & TEST CHALLENGES
Challenges and Developments in Reliability Testing
Computing power is increasing in semiconductor development. Which results in increasing energy dissipation of a DUT, raising of voltage levels and decrease of ESD voltage levels due to upscaling of package size. How can reliability tests be performed reliable on those devices? What is the impact on the current process and how can we stay ahead of these challenges? What is the effect of ESD protection on larger devices packages and how can we continue to ESD test those devices? And what is the impact of high-level voltages for reliability testing? A lot of challenges where Eurofins | MASER is working on to be ready for future reliability testing.
Biography
Wouter ter Laak is currently serving as the Reliability Department Manager of Eurofins | MASER. He earned his Bachelor in Electrical engineering from Saxion Hogeschool in Enschede, The Netherlands, in 2002. Following his graduation, he joined Texas Instrument as a EMC test Engineer. In 2004 he transitioned to Failure analysis Quality engineer in München region and 2007, Wouter promoted to Supervisor Failure Analysis location Almelo (Sensata technologies B.V. as of 2016). Expending his responsibilities as Supervisor of the Sofia analysis team in 2020. In 2021 he promoted to Reliability lab and Failure analysis Manager location Hengelo and started his role as Reliability Department manager of Eurofins | MASER begin 2022.
11:00–11:15
SHORT BREAK WITH VENDOR FAIR
11:15–11:45
IC DESIGN & TEST CHALLENGES
Testing a 2x25W class D output stage
Battery driven audio playback devices with high output power is an increasing market. Most of these systems have a plastic enclosure in which heat convection to the environment is limited. It requires high efficient class D power conversion to limit the power losses and temperature increase. A two channel Bridge Tied Load (BTL) power stage of this market will be presented that can deliver 2x25W in 4Ω loads and is packaged in a small QFN-28 package. The test program of this device is developed at Salland. A detailed explanation will be given of the gate oxide stress test and on-resistance test that are optimized by making use of dedicated embedded circuits.
Biography
Lûtsen Dooper was born in Leuvenheim, The Netherlands, in 1976. He received the B.S. degree in electrical engineering from the HAN University of Applied Sciences in 1999 and the M.Sc. degree in electrical engineering from the University of Twente in 2003. Currently he is working at Axign as system architect. His research interests include class D amplifiers and integrated power electronics.
11:45–12:15
IC DESIGN & TEST CHALLENGES
New Methods & Tools in MEMS/Photonic Testing
Silicon-based Devices other than ICs have varied working principles that go beyond the electronic: photonics, fluidics, MEMS, quantum etc. The utility of a given SBD from this group is usually tightly connected to what the manufacturing process can offer. Special functional (bio)layers, custom etched structures, buried flow channels, chip combinations and other non-standard features are usually needed for a product to exhibit its unique selling point at the end. It is therefore essential that testing - sometimes also referred as qualification - of such devices extracts information that goes beyond the one provided by only electrical contacting. In this presentation we couple the testing needs of non-IC SBDs to various potential probing methods and present the tools we are developing for that purpose.
Biography
Aleksandar Andreski
Dr. ir. Aleksandar Andreski (1978) graduated in 2003 from the Delft University of Technology with a specialization in Microelectronics. He worked at Phillips Semiconductors (now NXP) as a mixed-signal IC designer and obtained a PhD on the topic superconducting circuits from the University of Twente in 2011. In 2012, he became involved as a researcher and then project leader in the newly formed Applied Nanotechnology Research Group at the Saxion University of Applied Sciences. He collaborated with companies and other knowledge institutions on the application of Micro- and Nanosensors in the medical and agri-food sectors. From 2019, thanks to a NWO L.INT grant, he leads a group on MEMS/Photonic Probing, Testing and Reliability at the Saxion. In 2023 he joined part-time Salland Engineering as an R&D Scientist.
12:15–12:45
IC DESIGN & TEST CHALLENGES
Signal-chain noise application and challenges
One of the greatest challenges in designing a precision data acquisition measurement signal chain is managing and minimizing the noise. There are design trade-offs that balance the noise contribution of the different stages of the signal chain to establish the optimum signal conditioning solution between the sensor and the digitizer input. In this presentation, we will provide some background to these challenges before presenting our Noise Tool, a web-based tool designed to build, simulate, and verify complex precision signal chains. We will also announce the up-coming release of the lowest noise spectral density ADC on the market and go into detail on how Salland Engineering are enabling us to evaluate performance at the leading edge of technology.
Biography
Martin Walker has been an Applications Engineer in the semiconductor industry for 30 years. He joined Analog Devices in 2020 to support aerospace and defense customers with analog, mixed-signal, and power applications. In January, he moved to the Newbury Design Centre as a Lead Engineer for Product Marketing in Precision Converters Group, focusing on Precision with Speed and Compact Precision strategies. Martin graduated with a bachelor’s degree in electronics engineering from Southampton University.
12:45–13:30
LUNCH WITH VENDOR FAIR
13:30–14:00
TEST TECHNOLOGY & TOOLING
Tackling the quantum device testing bottleneck
Quantum computing has the potential to solve complex problems faster than classical computers. However, for practical commercial applications, we need quantum chips with more qubits that are of significantly better quality. To achieve this, we must explore novel approaches inspired by the mature semicon industry. Quantum chip testing in particular poses a significant bottleneck in realizing practical quantum computing. Here, we will explore the unique aspects of quantum testing compared to classical chip testing. In contrast to conventional CMOS metrology and testing, no simple correlations exist between conventional optical inspection and information processing parameters of a quantum chip. The full performance of a quantum chip can therefore only be measured by calibrating and tuning up the qubits to levels of quantum computing operating conditions. Superconducting as well as semiconductor-based quantum chips do not operate in ambient conditions, but need to be isolated and shielded, involving high vacuum, ultra-low (~20mK) temperatures, and low-power microwave electromagnetic signals. Tuning up qubits requires a framework for executing physics-based control sequences and protocols that also allow for the automation of the tasks usually performed manually by experienced quantum engineers. Join us to delve into the intricacies of quantum chip testing and understand its vital role in making quantum computing a commercial reality.
Biography
Thorsten is Co-Founder and Director of Development & Engineering at Orange Quantum Systems (OQS), a spin-off of QuTech in Delft, NL. Thorsten received his PhD in Electrical Engineering from the Ruhr University in Bochum, GER. He was involved in various projects spanning from “beyond CMOS” device physics to EUV lithography. Before co-founding OQS, Thorsten was part of the team who developed Quantum Inspire, Europe's first cloud-accessible quantum computer.
14:00–14:30
TEST TECHNOLOGY & TOOLING
Elevating Innovation in ATE Semiconductors
As quickly as the semiconductor industry evolves and advances, requirements for testing chips is also expanding at a rate that is challenging to keep up with. Testing Quick Charging, UCie standards, and automotive power, are industry challenges that ATE manufactures are facing and need to develop solutions for. With ElevATE’s new silicon strategy, modularity, future reuse, and time to market, we are driving our engineering decisions and paving the road for intelligent solutions to be developed. Chiplets, also known as heterogeneous integration, will be laying the foundation of the ATE future from both a tester integration perspective and an external testing perspective.
Biography
Matthew Getz is currently working at ElevATE semiconductor as a Product Marketing Engineer. With a decade of experience working in the ATE industry from jobs ranging from Test engineering to applications, Matthew is enjoying his work developing the roadmap for Elevate and shaping the future of ATE.
14:30–15:00
SHORT BREAK WITH VENDOR FAIR
15:00–15:30
TEST TECHNOLOGY & TOOLING
Visual Basic for Applications (VBA) to C-based test program conversion
Converting test programs between tester platforms is the first step for managing tester capacity. However, text-based programs and table-based programs have fundamental differences which usually requires lots of human efforts to look into the details. This session shares the approaches and potential methods to automate the conversion process. The preliminary result shows significant reduction in conversion time and much reduced test debugging efforts.
Biography
Dave Forsythe has over 20 years of experience in the field of semiconductor test specializing in mixed signal and RF test solution development. He has been employed at ATE companies and semiconductor companies which has developed a broad knowledge base. He has lead test development teams and implemented test development departments within organizations from scratch. Having worked for Chroma ATE for 2 years, Dave enjoys his customer facing role in the European applications engineering team. His aim is to build strong partnerships with his customers by providing swift resolution of customer issues as well as test implementation guidance on Chroma’s portfolio of test systems.
