PROGRAM
Thursday, February 13 (Day 2)
PRESENTATIONS
09:00–09:30
NEW PRODUCTS & TRENDS
Wafer Acceptance Testing: Leveraging Low Leakage Switching with Switched Guard Technology
Wafer Acceptance Testing (WAT) is essential in semiconductor manufacturing to ensure the quality, reliability, and performance of wafers. This process involves conducting precise electrical tests to evaluate device performance and requires the ability to measure extremely low-level currents, often in the sub-picoampere range, with high accuracy. Low-leakage switching and switched-guard technology are crucial for achieving this precision. Low-leakage switching minimizes parasitic currents, preserving the integrity of sensitive signal measurements. Switched-guard technology enhances accuracy by isolating high-impedance signals and driving the guard shield to the same voltage as the signal line, effectively eliminating capacitance effects and improving measurement reliability.
Custom reed relays optimized for switched-guard technology play a pivotal role in WAT. These relays offer ultra-low leakage currents in the femtoampere range and high isolation resistance exceeding 10¹² ohms, providing exceptional signal integrity and minimizing interference. This ensures precise, repeatable testing for wafer and chip-level measurements. Together, these technologies enable efficient and accurate WAT, supporting timely adjustments in semiconductor production. By providing reliable data for process optimization, they ensure high yields, superior product quality, and precise characterization of individual device pins, meeting the stringent demands of modern semiconductor manufacturing.
Biography
Noman Hussain is the Vice President of Strategic Business Development at Pickering Interfaces. Based in Colchester, GB, he is a recognized leader in the test and measurement industry, with a focus on advancing Automated Test Equipment (ATE) systems. Noman is instrumental in driving the growth and strategic vision of Pickering Interfaces, enabling the organization to deliver high-quality, efficient solutions that meet the evolving needs of its customers.
With a career spanning over a decade at Pickering Interfaces, Noman has held several key positions, including Software Manager and Software Engineer. His leadership extends beyond technical expertise, as he has played a significant role in aligning product development with market insights and fostering long-term client relationships.
Noman’s academic credentials include an MBA from Warwick Business School, an MSc in Computer Software Engineering from the University of Oxford, and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from the University of South Wales. His robust technical and managerial background, combined with a forward-thinking approach, ensures he consistently delivers on the mission of optimizing quality and efficiency in ATE systems.
09:30–10:00
NEW PRODUCTS & TRENDS
Evolution of PXI(e) Test for Digital Solutions
As AI, communications, EV and self-driving automobiles drive the need for greater data acquisition and processing, smaller and smaller geometries have been used to preserve cost, power and footprint. This places greater stress on testing these high pin count devices thoroughly and cost effectively. Meeting this challenge requires testers and instruments with greater pin counts, made possible by lower power, higher density pin electronics. Elevate has collaborated with Salland Engineering (Advantest), a top instrument manufacturer, to offer Pin Cards with 2x-4x the density, speed and memory of existing instruments with the same power and footprint. This paper will detail the design and performance of a modular 64-channel PXI(e) card and the device that enabled it. The modular design of these cards allow for the flexibility to expand the design as the market needs require.
Biography
Matthew Getz is an Applications manager at ElevATE Semiconductor, leveraging over ten years of experience in the Automated Test Equipment (ATE) industry. His career has covered Test Engineering and Applications, where he is now contributing to ElevATE's roadmap and the advancement of ATE technologies.
10:00–10:30
NEW PRODUCTS & TRENDS
Enabling the Industrialization of Quantum Technologies
Quantum technology is starting to emerge as a technology with a number of potential future applications. However, the developments of these technologies are still in its early stages – meaning that the technologies are not always ready yet to be picked up by industrial parties. At its essence, quantum technologies involve a quantum device – often a chip with micro- or nanoscopic features. These are manufactured in cleanroom facilities, and ultimately integrated into a complex system involving cryogenics and electronics to operate them. Demonstration of quantum technologies is regularly done in academic environments, where 1 device is ultimately sufficient to show the proof-of-principle. Nowadays however, the technology is starting to shift from academic to a more industrial environment. This requires more thorough testing, thus introducing a new set of challenges.
In this talk we’ll share what technical challenges we foresee in the manufacturing and testing of quantum devices – with a focus on semiconducting quantum devices. We’ll share how we intend to mature the technology further such that we can enable the industrialization of quantum technologies.
Biography
Yoram Vos is an applied physicist working at TNO, with a keen interest in working on challenging technologies that lie on the intersection of different disciplines. The past years he has worked on semiconducting quantum chips where different expertise such as nanofabrication, electronics and software engineering interleave. He has been involved in the designing, testing, and tuning of these quantum chips to ultimately run quantum algorithms by end users.
10:30–11:00
NEW PRODUCTS & TRENDS
A modular Equipment platform for Photonics Metrology
In response to the diverse needs of the photonics industry the MEKOPP consortium created a modular equipment platform for metrology applications. Proving a structure for effective integration of the expertise of the consortium partners, with sufficient flexibility to meet the needs of different product technologies and applications on their path from laboratory to high volume production.
A modular platform created from a production perspective, flexible yet robust, standardized yet prepared for customization. This presentation introduced the first two metrology systems based on this platform: visual inspection system HELIOS and optical-electronic wafer prober SIRIUS. Key technology providers, Nobleo for HELIOS’ AI based inspection software and Salland Engineering for SIRIUS’ test systems, will highlight their contributions.
Biography Ton Pothoven
With over 35 years of experience in production automation and innovation, Ton has built a solid base in the field of technology. After contributing to the semiconductor industry for 15 years, he spent 12 years in senior management positions within the hearing-aid transducer division of Sonion A/S. Ten years ago he joined IMS in the position of CEO, and recently stepped aside to completely put his focus on IMS’ ambitions in the photonics industry.
11:00–11:15
SHORT BREAK WITH VENDOR FAIR
11:15–11:45
AUTOMATED SILICON VALIDATION
Increase DAQ System Density and Throughput with Multi-channel Flexible-Input Simultaneous-Sampling ADCs
It is often assumed that analog-to-digital converters are high impedance. While it is true that direct sampling ADC architectures will often be high impedance when not converting, large input current spikes may occur at the beginning of a sample acquisition. The higher the sampling rate, the tougher challenge is to sufficiently settle this perturbance to within the ADCs resolution before the next conversion cycle. This requires high slew-rate drivers, meaning additional board complexity and power.
ADI addresses this challenge with its family of multi-channel, buffered high voltage SAR ADCs, which offer truly high impedance inputs that can accommodate different range of input signals, from 2.5V to 40V, configurable on a per channel basis. These buffers simplify or eliminate the need for signal conditioning in many cases, minimizing the board space and complexity, while achieving fast throughput rates. Being a SAR ADC, easy to synchronize, simplifies also scaling the system to larger channel count applications. A collection of circuits will be presented to demonstrate applications that take advantage of the properties of fully buffered ADC inputs.
Biography
Lluis Beltran Gil received his M.Sc. degree in industrial engineering in 2012, from the Technical University of Valencia. After graduation, Lluis joined Analog Devices in 2013 as an applications engineer in the Precision Converter Group in Limerick (Ireland). Since then, Lluis has been working on the Precision SAR ADC Applications Team supporting simultaneous sampling ADCs. He is currently based in Valencia, Spain.
11:45–12:15
AUTOMATED SILICON VALIDATION
Analog test signal generation for embedded ADCs in Radar ICs
The key requirement for ADCs used in the IF bandwidth of automotive radar ICs is SFDR (Spurious Free Dynamic Range). To test these ADCs the analog input signal must be highly linear. Moreover a coherent signal generation to the sampling clock of the ADC eases the post processing in the frequency domain. This presentation covers varies aspects for generating single or multi tone sine waves which meets above requirements.
Biography
Armin did 5 years of Higher Technical Institute for Mechanical Engineering in Klagenfurt (Austria); he worked 1 year as a CAD technician for building Services Engineering (www.ax3000-group.de ESS software service) and did 4 years of study at University of Applied Sciences for Electronic in Villach (Austria).
Since 2003, Armin is Component Validation Engineer at Infineon Technologies Austria in various R&D groups. He has experience in PLL measurements in time domain, ADC and DAC characterization in standalone testchip modules or embedded into µControllers or Radar ICs, characterization of embedded Die Temperature Sensors and partly also for amplifier ICs in Silicon Microphones for hearing aids.

Armin Schilke
Infineon Technologies
12:15–12:45
AUTOMATED SILICON VALIDATION
Design Automation Trends in the Age of AI
AI devices are driving unprecedented size and complexity, challenging companies to meet time-to-market demands. This presentation explores two key emerging trends: First-Time-Right Silicon and data automation. These trends are not only crucial for AI devices but are also applicable across various device types, offering valuable opportunities to enhance efficiency and productivity in any organization.
Biography
Bill Wymbs is the founder of Alliance ATE, where he currently serves as President & CEO. With four decades of experience in chip design and fabrication, Bill Wymbs has spent the last 20 years leading the developing of Velocity, a design automation software that ensures First-Time-Right Silicon and faster Time-to-Market methodologies through data automation, training, and analysis.
Bill Wymbs grew up in New Jersey and earned a BSEE from Rutgers University. A sports enthusiast and outdoor adventurer, Bill Wymbs enjoys hiking, mountain biking, and spending quality time with his wife, daughters, and their rottweiler, Harley.
12:45–13:30
LUNCH WITH VENDOR FAIR
13:30–14:00
GROUP PHOTO
14:00–14:30
AUTOMATED TEST
Test & Coverage for Spiking Compute SoC at the Sensor Edge
The rapid development of machine learning has resulted in increasingly complex and large models to satisfy demands of higher accuracy and wider-range of use cases. This exceeding growth rate of model computation surpasses efficiency gains realized through Moore and Dennard technology scaling, posing a practical limit to continued advancements with existing techniques. The capabilities and complexities of the current solutions are compounded by the challenges of adapting such methods in resource-constrained edge devices able to support pervasive and decentralized intelligence.
In this context, brain-inspired, neuromorphic spiking neural network (SNN) accelerators aim to i) enable sensor systems to deliver actionable, domain-specific information instead of raw data, bringing intelligence capabilities to resource-constrained devices, ii) facilitate high-potential use-cases operating in an always-on, event-driven fashion, and iii) accelerate development of energy-proportional sensor systems
Innatera's ambient edge compute SoC is a platform enabling applications at low power, latency and bill of material constrained use cases. Test for the SoC presents challenges of coverage vs cost optimization. SNN due to their inherent nature can reduce the complexity of the test. With this Innatera aims to come up with novel test methodology for neural network based SoC to scale the production of SoC at affordable cost.
Biography
Dr. Aditya Dalakoti received B.Tech in Electrical Engineering from Indian Institute of Technology, Ropar in 2014, and MSc and PhD in Mixed-Signal VLSI from University of California Santa Barbara in 2016 and 2018, respectively. He has co-authored 10 papers in various IEEE conferences and Journals. He was previously with the LiDAR design division of Continental in Carpinteria, California where he was involved in the ReadOut ASIC design projects from 2018 to 2020. He later moved to the Netherlands to join Innatera in 2020. As Principal Engineering Manager, Dr. Dalakoti has led ground-breaking technical developments across Innatera's analog-mixed signal computing technology portfolio.
14:30–15:00
AUTOMATED TEST
Emerging PMIC Trends Demand Test Innovations
This presentation will discuss the trends and requirements driving PMIC innovation and test solutions that maximize yield for high quality chips at the lowest cost of test.
Power Management Integrated Circuits (PMICs) are responsible for managing the power requirements for mobile systems while preserving the battery charge. New innovations in mobile PMIC devices such as integrating chargers makes a single device responsible for handling a plethora of requirements such as different charging schemes, modes and inputs, including wall, USB, and wireless.
This component has become increasingly complex and embeds not only low drop out regulators, multi-phase DC-DC converters, USB fast chargers, general purpose analog to digital converters and communication interfaces but also other optional blocks such as LEDs, drivers, fuel gauges, and audio analog to digital / digital to analog converters. Testing high-performance PMICs requires high-density DC instruments with highly flexible merging capabilities to achieve high current.
Biography
Thomas Koehler is the Product Marketing Strategist for the Automotive end-market and Complex DC device segment at Teradyne. Before joining Teradyne's marketing team, he held several different roles in Application Engineering. Thomas Koehler received his diploma from Munich University of Applied Sciences. He is based in Munich, Germany.
15:00–15:30
AUTOMATED TEST
Paradigm shift of the test for AI chips
We have seen a paradigm change in making AI chips, from driving semiconductor process node to 18A and lower and the combination of chiplets using advanced packaging. Lots of new technologies have been brought to the world to make the new AI world possible. There is also a paradigm shift in testing of those super chips. Traditional wafer test and final package test followed by system level test and burn-in, and in conjunction with chained chiplet-to-chiplet tests, and this is driving changes in the test methods and critical test items in different stages. We will talk about how our thoughts to help customers maximize test coverage and improve product quality.
Biography
Eugene Lin is the vice president in Chroma’s semiconductor test business unit. Eugene spent more than 25 years in automated test system with different roles in marketing and R&D. Prior to joining Chroma, Eugene was product marketing manager in Keysight Technologies for new automated test platforms for more than 10 years. He is especially interested in designing new test solutions for the fast changing world. Eugene holds an MBA degree from National ChengChi University in Taiwan and Bechelor of Electrical Engineering from National Tsinghwa University in Taiwan. He likes playing violin during his leisure time.
15:30–16:15
AUTOMATED TEST
Generative AI Test Challenges & V93000 Solution
High performance compute devices (XPUs) are the silicon workhorses behind the AI revolution. Installed in large quantities in data centers, they power Open AI‘s ChatGPT, Microsoft‘s CoPilot, and countless other digital assistants and AI-enhanced software applications. These devices are typically on the edge of what is technically possible: Transistor count, energy consumption and quality requirements challenge even the most advanced production test environments. The majority of them is tested on Advantest‘s V93000 EXA Scale generation.
This presentation will give a brief overview of the most common building blocks of AI devices and of the V93000 components used to test them. Some details on power delivery, high-speed test data access and domain-specific extensions for HPC devices will be provided.
Biography
Michael Braun is Product Marketing Manager at Advantest Europe GmbH.
Michael has over 25 years experience in the ATE industry and holds a Master's degree in electronic engineering from the University of Mannheim, Germany. Within Advantest he started as a Dft & Application consultant and has several years experience as a Solution Architect in R&D and with EDA collaboration. Currently he holds the position of Product Marketing Manager with focus on high-speed digital & structural test.
16:15–16:45
AUTOMATED TEST
Increasing the quality of your in-system test
As the Semiconductor industry continues to change and evolve, requirements for test continue to extend from manufacturing into in-system as part of a growing SLM strategy. The growing need to increase the quality of in-system testing capabilities is driving a shift in technology.
Thanks to new innovation, it is now possible to apply manufacturing quality test patterns direct to a design, leveraging the benefits of deterministic test over transitional in-system test methods.
Biography
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 20 years of industry experience with Siemens Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.
16:45–17:30
CLOSING DRINKS