PROGRAM
Wednesday, February 12 (Day 1)
PRESENTATIONS
09:30–10:00
KEYNOTE
Sallands vision on the Evolution of Test
Opening of the Symposium and welcome speech by Paul van Ulsen, CEO and owner of Salland Engineering, where he will share Salland's vision on the evolution of semiconductor test.
Biography
Paul has over 37 years’ experience in Semiconductor Test and is currently responsible for all aspects of corporate governance and business development for Salland Engineering worldwide. He is a graduate of Windesheim Technical University in electronics and computer engineering.
In 1986, Paul started his career as Test Application engineer at Rood Testhouse, where he was involved in many Mixed Signal test solutions. In 1992, he continued as Application engineer at Salland and moved soon into new roles like; project management, HR and Sales which made him decide to choose to be the Sales Director, followed becoming the CEO and in 2017 the owner of Salland Engineering world-wide. In 2018 he acquired Applicos, a leading Analog post-silicon-validation test solution provider, and successfully integrated this into Salland family. In meantime he guided Salland, together with his team, being a worldwide leading and respected player & partner of all top ATE manufactures and being a very advanced and fast(est) growing Engineering & Production Testhouse.
10:00–10:30
IC DESIGN & TEST CHALLENGES
Defining industrial quantum chip testing
To realize useful quantum computation, orders of magnitude more, and better, qubits are needed. To realize this, we need to establish rapid feedback cycles between the fabrication, design, and characterization of quantum chips. Historically, the same systems have been used to do research on quantum devices, provide feedback to characterization, and even function as quantum computers. As the technology matures this approach is running into its limitations and testing is becoming the bottleneck in the development process. In this talk we take a systems engineering approach to reimagine what a quantum test system should be and go over the design process and realization of the OrangeQS MAX, the world’s first industrial quantum chip test system capable of testing 150Q + quantum chips.
Biography
Adriaan Rol is one of the founders and directors of Orange QS. Adriaan holds a PhD (cum laude) from Delft University of Technology. His work on the control for programmable superconducting quantum systems in the group of Prof. dr. Leo DiCarlo (QuTech/Delft University of Technology) forms a fundament under the test systems of OrangeQS. He has developed new calibration and characterization protocols, as well as a new type of two-qubit gate, made key contributions to the development of QuTech’s Quantum Inspire platform (Europe’s first quantum computer), and served as the liaison to the IARPA LogiQ Test and Evaluation team. Adriaan has worked closely with experts from all layers of the stack, which was formally recognized through the Zurich Instruments Pioneer Award and resulted in award-winning papers. Before starting his PhD, Adriaan was on the executive board of a non-profit business consultancy.
10:30–11:00
IC DESIGN & TEST CHALLENGES
Breaking the Defect Barrier: The Evolution and Future of VLSI Testing with Device-Aware Methods
Functional testing, the original method for testing VLSI chips, quickly became inefficient and costly as circuit complexity grew. This prompted the development of structural testing techniques in the late 1960s and early 1970s. Over time, advancements in technology scaling and the emergence of new device technologies have significantly enhanced structural testing. However, despite these improvements, achieving a zero-defect rate (i.e., zero defects per million) remains a challenging and elusive goal. For example, Meta recently reported that their computing infrastructure is affected by silent data corruptions (SDCs), where computing devices inadvertently produce errors, such as incorrect results, without being detected. At the most recent International Test Conference, Meta revealed that approximately 80% of these SDCs were linked to hardware failures, highlighting the limitations of current testing methodologies.
This talk will explore the historical evolution of structural VLSI testing, from the introduction of the stuck-at fault model to the development of the cell-aware test methodology. It will also address the limitations of current approaches in achieving defect-free production. A novel approach, Device-Aware Testing (DAT), developed at TU Delft since 2019, will be introduced. Through industrial case studies, we will demonstrate DAT’s ability to identify realistic faults and detect unique defects that traditional methods fail to capture. Moreover, DAT provides valuable insights for enhancing automated test equipment (ATE), incorporating innovative features that reduce test costs and improve product quality. For example, we will showcase how integrating a magnet into ATE significantly improves test coverage and reduces test time for STT-MRAMs, with these advantages validated through silicon measurements. Finally, the talk will discuss future challenges and potential breakthroughs in VLSI testing methodologies.
Biography
Said Hamdioui is Chair Professor of Dependable and Emerging Computer Technologies at Delft University of Technology (TU Delft), where he also leads the Computer Engineering Laboratory. He co-founded Cognitive-IC, a startup specializing in hardware dependability solutions, and served as Head of TU Delft's Quantum and Computer Engineering Department (2019–2023). His research focuses on emerging technologies and computing paradigms (e.g., memristors, in-memory computing, brain-inspired computing) and hardware dependability (testability, reliability, and security).
Hamdioui earned his MSEE and PhD from TU Delft and gained industry experience at Intel, Philips, and NXP. He holds four patents, authored/co-authored three books, and published 330+ papers. He has provided training and consulting to major semiconductor companies like Intel, NXP, STMicroelectronics, Renesas, and Huawei.
Hamdioui has received numerous accolades, including the EDAA Outstanding Dissertation Award, European Commission Innovation Award, and over 20 Best Paper Awards. He has been a Distinguished Lecturer for IEEE, an editor for leading journals, and an active member of international research committees. Recognized among the world’s top 2% scientists (Stanford & Elsevier 2024), Hamdioui’s contributions significantly influence the semiconductor and EDA industries. He is a Senior IEEE Member and a Fellow of The Netherlands Academy of Engineering.
11:00–11:15
SHORT BREAK WITH VENDOR FAIR
11:15–11:45
IC DESIGN & TEST CHALLENGES
AI processor test and characterization requirements
With interest and competition in Artificial Intelligence (AI) processor space increasing rapid, bring-up and prototyping is becoming critical to success in the market. A high degree of parallelism is not only required for the processor itself but also in the approach to the new product introduction (NPI) plan.
This presentation will give an overview of the main features of an AI processor and its test and characterisation requirements. This will include an overview of tools and methodology used for rapid bring-up. Some of the key challenges for characterisation will be discussed, particularly for applications in the edge AI market where performance at low power consumption is key. An overview will also be included of the application space of edge AI systems, particularly vision systems for automation of inspection and quality control.
Biography
Mark Dellow is Product Engineering Manager at Axelera AI. Mark is a device physicist by training and has nearly 30 years experience working in the industry. He started off as a device and process integration engineer working in wafer fabs and later migrated to foundry interface, product test and characterisation with fabless chip companies. More recently working with several smaller companies and start-ups in the Bristol area of the UK.
11:45–12:15
IC DESIGN & TEST CHALLENGES
Challenges and Opportunities in Testing of Integrated Photonics
Integrated photonics provides diverse functions that enable unprecedented data throughputs, and energy efficiency at the chip level. Frequently generalized as silicon photonics inevitably becomes a part of the microelectronics industry and enters large-scale semiconductor supply chains. The latter is mainly stimulated by aggressive demands from data centers and high-power computing (HPC) infrastructures supporting more, and more used artificial intelligence (AI).
Test processes for integrated photonics have been identified as some of the top contributors to the manufacturing cost, and become even more critical when positioning photonics as a part of the high-volume manufacturing (HVM) semiconductor industry. This urges a need for highly automated, standardized solutions for electronic-photonic testing, which can scale and match the pace of production flows in the HVM supply chain. The Integrated photonics and electronic-photonic test have become standing topics on the agenda in global technology roadmaps such as Integrated Photonic System Roadmap International (IPSR-I, Nanophotonics center MIT and PhotonDelta), and Heterogeneous Integration Roadmap (HIR), by IEEE and Semi, and many standardization efforts for example by IEEE SA Photonics Committee. The Dutch high-tech industry and R&D organizations are deeply involved in photonics and play a pivotal role in providing leading-edge solutions and shaping the roadmaps for integrated photonics at the global scale.
The current perspective, future outlook, and some development highlights from the Photonic Integration Technology Center will be presented.
Biography
Dr. Sylwester Latkowski.
Sylwester Latkowski shares his duties at the Eindhoven University of Technology (TU/e) with the position of Scientific Director at the Photonic Integration Technology Center, a Dutch applied R&D organization, set up by TU/e, UTewnte, TNO, and PhotonDelta. He also leads the PITC Metrology Program, working closely with the industry on the next-generation test solutions. His professional activities include an active role in road-mapping initiatives such as IPSR-I and HIR, in which he is a chair, co-chair, and contributor of the electronic-photonic test chapters. Sylwester is representing PITC on the steering committee of JePPIX. He is a senior member of the IEEE and a voting member of the IEEE Standards Association Photonic Standards Committee. He chairs the working group for the standardization of electronic-photonic design automation.
12:15–12:45
IC DESIGN & TEST CHALLENGES
To-test, or not-to-test: balancing between costs of testing and quality
To-test or not-to test, that is the dilemma in electronic manufacturing services (EMS). This narrative poses a critical challenge, especially in the realm of printed circuit board assembly (PCBA). Comprehensive testing and visual inspections are an integral part of the PCBA process to ensure that boards are free of assembly faults or failures, provided the design itself is error-free. However, the increasing demand from customers for exhaustive testing protocols introduces a complex trade-off. While these additional tests can enhance test coverage, they come with significant costs in terms of time, resources, and incurred expenses. This paradox raises the fundamental question: does the incremental assurance provided by extensive testing justify the associated operational inefficiencies and financial burdens? Balancing cost-effectiveness, time-to-market, and customer satisfaction is pivotal in determining the optimal testing strategy. Simulation and prediction tools based on statistical analysis, design rules and first product inspection can be beneficial to ensure reliability while remaining commercially viable. This paper discusses the decision-making process, exploring the need for strategic approaches that align quality assurance with manufacturing efficiency.
Biography
Ercan Sengil is a Business Development Manager at Philips Micro Devices (Greenhouse), located at Strijp-S Eindhoven, the historical innovation playground of Philips. He started his career in 1996 at Philips Semiconductors as an RF Power engineer, and held various marketing, sales, and key account management roles at Philips Semiconductors, NXP Semiconductors, Philips Healthcare, and Infineon Technologies. From 2020 to 2022, he was a lecturer at Fontys University of Applied Sciences. Ercan returned to Philips in 2022 as a Sales and Business Development Manager. He holds a BSc in Eelctrical Engineering from HAN University of Applied Sciences and an MBA from Bryant University.
12:45–13:30
LUNCH WITH VENDOR FAIR
13:30–14:00
TEST TECHNOLOGY INNOVATIONS
ESA TRUTHS Radiometer Electronics: Testing Methodologies for Electronics Development and Characterization
The presentation will provide a comprehensive introduction to the institute, emphasizing its extensive expertise and proven experience in the design and calibration of precision radiometers. These instruments play a critical role in advancing the understanding of solar measurements and their impact on Earth’s climate.
The presentation will also explore the fundamental principles of TSI (Total Solar Irradiance) measurements, discussing their significance in quantifying the Sun’s total energy output across all wavelengths and their role in assessing solar variability and climate change effects.
Additionally, the presentation will outline the requirements for the next reference instrument that will be deployed onboard the ESA TRUTHS mission. This next-generation instrument will be a key component in providing accurate and reliable solar irradiance measurements for climate monitoring and Earth observation.
Finally, the presentation will delve into the specialized measurement setups and testing methodologies necessary to ensure that these instruments meet the stringent accuracy and long-term reliability standards required for the TRUTHS mission. This will include an overview of precision calibration processes, performance validation techniques to ensure the instrument's performance over extended periods.
Biography
Manfred Gyo studied electronics at FH Aachen, laying a strong technical foundation for a dynamic engineering career. He began in the automotive industry, focusing on measurement systems for quality control, before advancing into roles in traffic measurement and control systems as a development engineer and project manager. Since 2011, he has been a member of PMOD/WRC, serving over years as Head of the Technical Department and Project Manager. He led the Swiss contribution for the EUI and SPICE instruments on the ESA/NASA Solar Orbiter mission. Manfred Gyo now leads the development of the electronics for a reference radiometer for solar irradiance measurements.
14:00–14:30
TEST TECHNOLOGY INNOVATIONS
Photonics Following Semiconductor Manufacturing’s Path
The good news is that applications of photonics are sprouting like desert flowers after a rain. The bad news is that the numbers add up to a thousand-fold step-function in industry productivity. How can we achieve this torrid pace? Whether the challenge is to accommodate new applications for billions of ever-higher-quality cameras, or to package and deploy next-generation AI chips with photonic connections to high bandwidth RAM and parallel resources, or to simply keep up with humanity’s insatiable appetite for connectivity, the trends are turning relentlessly vertical. And yield and losses must be addressed, painfully costly processes must be attacked, and that three-order-of-magnitude increase in productivity must be scaled, all at the same time.
In this talk we identify some commonality among the challenges presented by the diverse applications and technologies the photonics world is pursuing. It turns out there are not just processes, tools and substrates to borrow from semiconductor manufacturing, but lessons as well. When dovetailed with novel technologies that address stubborn pain-points common to the manufacturing and testing of photonic devices of all sorts, the insights are truly enabling for an industry that finds itself on the launching pad without a flight plan. We close with some success stories from the emerging ecosystem and a look at the hopeful future we can now anticipate.
Biography
Scott is a businessman and physicist by training, with an MBA in Finance and New Venture Management. He has driven multiple business development and turnaround endeavors. He is Head of Photonics for PI, the global leader in ultra-precision automation.
Scott developed the first digital gradient search, still widely used and fundamental to photonics test and packaging, and established a successful business upon it. He has repeatedly driven the field forward as device designs have advanced. His recent work enables one-step, global alignment optimization across multiple elements, inputs, outputs and degrees of freedom of today’s photonic and tomorrow's quantum devices. By speeding the alignment process by a factor of 100, this is a proven enabler for manufacturing economics.
A confirmed technology evangelist, Scott publishes and presents frequently. He was named a PI Fellow in 2016.
14:30–15:00
SHORT BREAK WITH VENDOR FAIR
15:00–15:30
TEST TECHNOLOGY INNOVATIONS
Benefits of combined Electrical and Optical Test on small devices & the added value of Artificial Intelligence on Optical Inspection
This presentation will review both the handling of (very) small components where multisite electrical test can be combined with optical inspection, and, the use of Artificial Intelligence to significantly reduce over-rejection (the loss of good devices) when screening for small defects. In the first section, we explain how Neon combines multiple process steps into one by combining multisite electrical test with high-end optical test. This is particularly important for very small devices where handling steps need to be minimized. Also, there will be a saving on transport medium (typically filmframe) between electrical and optical test. In the second section, we explain how Artificial Intelligence distinguishes between genuine defects and acceptable imperfections such as scratches or dust particles. Without the assistance of AI, many good devices would become rejected unnecessary, impacting daily output and revenue. We invite you to join us at the conference for a deeper exploration of these capabilities.
Biography
With over two decades of experience in the semiconductor industry, specializing in Turret handlers & Optical inspection systems since 2000, Raul Arriola has held several key positions in the area of Optical Inspection Department (Vision), Product Management (Handlers & Modules), Technical Product Specialist (Turret) and Strategic Business Development (Turret & Inspection). Some of his key achievements over the years:
- Established the Asia Vision Department for on-site support
- Led the Vision department setup of a new manufacturing facility in Malaysia (Turret)
- Served as Product Manager for the next-generation turret handler (NY20)
- Created the Technical Product Specialist Group for the sustainment of high-tech turret products
- Patented Next-Gen Turret Test process Maximizing system UPH without any additional ATE resources
Currently, Raul holds the position of Business Development Manager at Cohu.
15:30–16:00
TEST TECHNOLOGY INNOVATIONS
A Tester on a Probe Card
With forecasts for chiplets showing tremendous growth, what's driving driving chiplet growth and what are the potential impediments. We suggest that a tester on a probe card approach might help remove a barrier to chiplet growth.
Biography
Patrick Sullivan has designed ATE semiconductors for over 30 years. He was a cofounder of Edge Semiconductor, Planet ATE and in 2012 he co-founded Elevate Semiconductor where he was CEO until 2020. Patrick currently sits on the Elevate Board of Directors and consults in technology development.